The present invention relates to a television receiver for receiving conventional television signals of the NTSC system or PAL system or high-quality television signals such as multiple sub-nyquist sampling encoding (MUSE).
As the high-quality television system with an aspect ratio of 16:9 has come into wide use, various examinations have been made for compatibility with the standard television system which is the conventional NTSC system.
When an image by a video signal with an aspect ratio of 4:3 is displayed as it is on a display screen with an aspect ratio of 16:9 for example, a circle is displayed as an ellipse which is long sideways as shown in FIG. 5(a). Therefore, the video signal is generally processed so that the image is compressed horizontally as shown in FIG. 5(b), and the image is displayed with a side blank signal inserted on both left and right sides.
According to this display method, however, there are parts with no image displayed on both sides of the display screen, and the wide screen with an aspect ratio of 16:9 is not used effectively. Therefore, a technique for enlarging and displaying an image vertically as shown in FIG. 5(c) by processing a video signal with an aspect ratio of 4:3, and for using the display screen effectively is indicated. An example of a conventional television receiver of the NTSC system for obtaining such an image will be explained with reference to FIG. 6. In the figure, numeral 1 indicates a UHF/VHF antenna, 2 a UHF/VHF tuner (hereinafter called a front end (FE)) including an interface circuit, 3 an NTSC decoder, 4 a conversion circuit for display area or picture converter, 5 a signal processing circuit, 6 a cathode-ray tube, 7 a micro computer, 8 a remote controlled signal acceptor, 9 a key switch, and 10 a video chroma processing circuit.
In FIG. 6, the aspect ratio of the display screen of the cathode-ray tube 6 is 16:9. Assuming that the front end 2 is set so as to select video signals of the NTSC system (hereinafter called NTSC signals) among received signals from the antenna 1, the NTSC signals are supplied to the video chroma processing circuit 10. This video chroma processing circuit 10 consists of the NTSC decoder 3 and picture converter 4, and the NTSC decoder 3 and picture converter 4 change their operations according to instructions from the remote controlled signal acceptor 8 or the key switch 9 of the keyboard via the micro computer 7.
Upon reception of an instruction to receive NTSC signals from the remote controlled signal acceptor 8 or the key switch 9, the front end 2 operates so as to select NTSC signals as mentioned above, and the NTSC decoder 3 operates so as to decode supplied NTSC signals. By doing this, in the NTSC decoder 3, NTSC signals are decoded and luminance signals Y and chrominance signals R-Y and B-Y are outputted and supplied to the picture converter 4. In response to an instruction from the remote controlled signal acceptor 8 or the key switch 9 the picture converter 4 processes the luminance signals Y and chrominance signals R-Y and B-Y as described below to display images by one of the methods shown in FIGS. 5(b) and 5(c) under the control of the micro computer 7. The output of circuit 10 is applied to the signal processing circuit 5 shown in FIG. 6. The signal processing circuit 5 processes the luminance signals Y and chrominance signals R-Y and B-Y so as to generate primary color signals, which are supplied to the cathode-ray tube 6 of FIG. 6. By doing this, on the display screen of the cathode-ray tube 6, an image of NTSC signals is displayed as shown in FIG. 5(b) or 5(c).
When high-quality television signals with an aspect ratio of 16:9 are received, video signals outputted from the front end 2 if FIG. 6 are processed by another video chroma processing circuit which is not shown in the drawing. The output of this other video chroma processing circuit is supplied to the signal processing circuit 5 shown in FIG. 6.
The picture converter 4 of FIG. 6 is a main part of the video signal processing for displaying images as explained in the description of FIG. 5.
FIG. 7 is a block diagram showing the video chroma processing circuit 10 of FIG. 6, which consists of the NTSC decoder 3 of FIG. 6, and the picture converter 4.
In the FIG. 7, reference number 12 indicates an input terminal, 13 an output terminal, 14 a non-interlace converting circuit, 15 and 16 memory circuits, 17 a digital interpolation filter, and 18 and 19 selection circuits. NTSC signals are inputted from the input terminal 12 and supplied to the NTSC decoder 3 of FIG. 7 so as to be converted to luminance signals and chrominance signals. These signals are converted to non-interlace signals by the non-interlace conversion circuit 14 and are scanned sequentially. Output signals of the non-interlace conversion circuit 14 are supplied to the memory circuits 15 and 16 and to the "a" side of the selection circuit 18 (switch).
When displaying an image of an aspect ratio of 4:3 by inserting side blank signals on the left and right sides of the display screen as shown in FIG. 5(b), the "a" side of the selection circuit 19 of FIG. 7 is closed and an output signal from the non-interlace conversion circuit 14 of FIG. 7 is processed by the memory circuit 15 and supplied to the signal processing circuit 5 of FIG. 6 from the output terminal 13. In this case, the memory circuit 15 of FIG. 7 makes the frequency of the read clock frequency higher than the frequency of the write clock, and compresses the time base of a video signal so that the period of the video section during each horizontal scanning period of the video signal is shortened. By doing this, the image display shown in FIG. 5(b) is made possible.
If a video signal which is an NTSC signal in which the aspect ratio is 16:9, an image is compressed horizontally so that, for example, an image which is circular originally is displayed as an ellipse which is longer than it is wide as shown in FIG. 5(d). In the case of such a video signal, the selection circuit 18 (switch) of FIG. 7 is closed on the "a" side, and the selection circuit 19 (switch) of FIG. 7 is closed on the "b" side, and an output signal of the non-interlace conversion circuit 14 of FIG. 7 which is generated and supplied to the signal processing circuit 5 of FIG. 6 by way of the output terminal 13. By doing this, as shown in FIG. 5(e), an image which is precisely shaped is displayed on a screen with an aspect ratio of 16:9.
Furthermore, when displaying an image on a display screen with an aspect ratio of 16:9 as shown in FIG. 5(c) using a general NTSC signal, the selection circuits 18 and 19 (switches) shown in FIG. 7 are both closed on the "b" side, and the memory circuit 16 having a large capacity is used. In this case, such an NTSC signal image is separated (extracted) by removing the upper and lower parts, and the remaining part is enlarged in the perpendicular or vertical direction. In the memory circuit 16 of FIG. 7, the picture area indicated by the NTSC signal is set as shown in FIG. 5(c) and the time base is corrected so that the solid line part in this picture area is separated for each screen of the video signal and enlarged perpendicularly or vertically. Although the number of lines (the number of horizontal scanning lines) is reduced by this separation, the reduced lines are interpolated by the digital interpolation filter 17 of FIG. 7. The video signal which is processed like this is supplied to the signal processing circuit 5 of FIG. 6 from the output terminal 13 via the selection circuits 18 and 19 of FIG. 7.
The aforementioned processing circuit consisting of the noninterlace converting circuit 14 and memory circuits 15 and 16 of FIG. 7 is provided for each luminance signal Y and chrominance signals R-Y and B-Y, and each signal is processed as mentioned above.
FIG. 8 is a block diagram showing the concrete configuration of the digital interpolation filter 17 of FIG. 7. In the drawing, number 20 indicates an input terminal of video signals from the memory circuit 16 of FIG. 7, 21 an output terminal, 22 "a" line delay memory, 23 and 24 multipliers of input signals, and 25 an adder.
Next, the operation of the digital interpolation filter 17 of FIG. 7 will be explained in detail with reference to FIG. 9.
(1) shown in FIG. 9 indicates sequential lines a, b, - - - in the aforementioned picture area in the memory circuit 16 of FIG. 7 and (2) shown in FIG. 9 indicates lines a, .circle. a' , .circle. b' , - - - of video signals outputted from the digital interpolation filter 17 of FIG. 7 which are line-interpolated, enlarged, and outputted. To prevent an image by the video signal obtained by this line interpolation from an unnatural image, the center of gravity of each of the dashed code lines such as lines .circle. a ' and .circle. b' is shifted vertically sequentially. In this drawing, an example of enlargement of 4/3 times is shown. Therefore, the center of gravity is shifted in units of 1/4. Between (1) of FIG. 9 and (2) of FIG. 9, interpolation tap coefficients are shown so as to set the aforementioned centers of gravity. The drawing shows that, for example, the line .circle. a' can be obtained by adding the line a which is multiplied by a tap coefficient of 1/4 to the line b which is multiplied by a tap coefficient of 3/4.
In the case of enlargement of 4/3 times as mentioned above, an enlarged video signal (for (1) as shown in FIG. 9) consisting of the lines in FIG. 9 can be generated by filtering of comparatively simple coefficients. This will be explained hereunder.
(3) shown in FIG. 9 indicates sequential lines which are inputted into the input terminal 20 of FIG. 8. The memory circuit 16 of FIG. 7 assumes the above picture area as a part of 3/4 of the original screen and reads the lines within this range sequentially, though it reads the same line repeatedly two times at every third line. In (3) shown in FIG. 9, for example, the line a is read two times, and the line b and line c are read once next, and then the line d is read two times. By doing this, one line is increased for each three lines and the number of lines on the entire screen becomes the regular number (for example, of the NTSC system). (4) shown in FIG. 8 indicates coefficients k.sub.1 of the multiplier 24 by which video signals of lines which are inputted from the input terminal 20 of FIG. 8 are multiplied. (5) shown in FIG. 9 indicates lines which are outputted from the line memory 22 ((3) of FIG. 9 is delayed) to which lines from the input terminal 20 of FIG. 8 are supplied. (6) of FIG. 9 indicates coefficients k.sub.2 of the multiplier 23 for lines outputted from the line memory 22 of FIG. 8. (7) shown in FIG. 9 indicates output signals from the adder 25.
The vertical enlarging process of each line shown in (2) of FIG. 9, is the process indicated by (3) to (7) of FIG. 9, which are indicated by a dotted line arrow. For example, the line .circle. a' is obtained by adding the line b which is inputted from the input terminal 20 and multiplied by a coefficient of 3/4 by the multiplier 24 to the line a, which is inputted from the input terminal 20 previously, outputted from the line memory 22, and multiplied by a coefficient of 1/4 by the multiplier 23 by the adder 25. The coefficients k.sub.1 and k.sub.2 of the multipliers 23 and 24 are changed sequentially for each line, and the centers of gravity of four lines consisting of three lines are not one-sided and uniform.
As mentioned above, this conventional example is advised so as to display a video signal with an aspect ratio of 4:3 effectively on a display screen with an aspect ratio of 16:9.
According to the above prior art, however, when displaying, for example, an image of a video signal with an aspect ratio of 4:3 on a display screen with an aspect ratio of 16:9, the display shown in FIG. 5(b) and the display shown in FIG. 5(c) can be changed. In this case, the image is enlarged and displayed as showed in FIG. 5(c) by using the memory circuit 16 and digital interpolation filter 17 of FIG. 7. An image which is displayed without being enlarged is shown in FIG. 5(b), where the contrast and sharpness are lost, and the image is apt to be seen as an image which is not modulated, and in which the image quality is changed. Therefore, to obtain a most suitable image quality in either of the image display modes shown in FIGS. 5(b) and 5(c), it is necessary to let the micro computer 7 of FIG. 6 control the signal processing circuit 5 of FIG. 6 by operating the key switch 9 or the remote controlled signal acceptor to change the display mode and to readjust the video control data such as the sharpness and contrast. It is not easy to operate the receiver, and when the display mode is changed, a sense of incompatibility may be caused due to a change in the image quality.